Flash memory is a commonly used type of non-volatile memory in widespread use as mass storage for consumer electronics, such as digital cameras and portable digital music players for example. The density of a presently available Flash memory chip can be up to 32 Gbits (4 GB), which is suitable for use in popular USB Flash drives since the size of one Flash chip is small.
FIG. 1 is a general block diagram of one bank of a known NAND flash memory. Those skilled in the art will understand that a flash memory device can have any number of banks. Bank 30 is organized into k+1 blocks. Each block consists of NAND memory cell strings, having up to i+1 flash memory cells serially connected to each other. Accordingly, wordlines WL0 to WLi are connected to the gates of each Flash memory cell in the memory cell string. A string select device connected to signal SSL (string select line) selectively connects the memory cell string to a bitline, while a ground select device connected to signal GSL (ground select line) selectively connects the memory cell string to a source line, such as VSS. The string select device and the ground select device are n-channel transistors. There are j+1 bitlines common to all blocks of bank 30, and each bitline is connected to one NAND memory cell string in each of blocks [0] to [k]. Each wordline (WL0 to WLi), SSL and GSL signal is connected to the same corresponding transistor device in each NAND memory cell string in the block. As those skilled in the art should be aware, data stored in the flash memory cells along one wordline is referred to as a page of data.
Connected to each bitline outside of the bank 30 is a data register 32 for storing one page of write data to be programmed into one page of flash memory cells, or read data accessed from the flash memory cells. Data register 32 also includes sense circuits for sensing data read from one page of flash memory cells. During programming operations, the data registers perform program verify operations to ensure that the data has been properly programmed into the flash memory cells connected to the selected wordline. Each memory cell of bank 30 can store a single bit of data or multiple bits of data. Some flash memory devices will have more than one set of data registers to increase throughput.
The advent of 8 mega pixel digital cameras and portable digital entertainment devices with music and video capabilities has spurred demand for ultra-high capacities to store the large amounts of data, which cannot be met by the single Flash memory device. Therefore, multiple Flash memory devices are combined together into a memory system to effectively increase the available storage capacity. For example, Flash storage densities of 20 GB may be required for such applications.
FIG. 2 is a block diagram of a prior art flash memory system 10 integrated with a host system 12. Flash memory system 10 includes a memory controller 14 in communication with host system 12, and multiple non-volatile memory devices 16. The host system will include a processing device such as a microcontroller, microprocessor, or a computer system. The Flash memory system 10 of FIG. 2 is configured to include one channel 18, where memory devices 16 are connected in parallel to channel 18. Those skilled in the art will understand that the memory system 10 can have more or less than four memory devices connected to it.
Channel 18 includes a set of common buses, which include data and control lines that are connected to all its corresponding memory devices. Each memory device is enabled/disabled with respective chip select signals CE#1, CE#2, CE#3 and CE#4, provided by memory controller 14. The “#” indicates that the signal is an active low logic level signal. The memory controller 14 is responsible for issuing commands and data, via the channel 18, to a selected memory device based on the operation of the host system 12. Data read from the memory devices is transferred via the channel 18 back to the memory controller 14 and host system 12. Operation of flash memory system 10 is synchronized to a clock CLK, which is provided in parallel to each memory device 16. Flash memory system 10 is generally referred to as a multi-drop configuration, in which the memory devices 16 are connected in parallel with respect to channel 18.
In Flash memory system 10, non-volatile memory devices 16 can be identical to each other, and are typically implemented as NAND flash memory devices. Those skilled in the art will understand that flash memory is organized into banks, and each bank is organized into blocks to facilitate block erasure. Most commercially available NAND flash memory devices are configured to have two banks of memory.
There are specific issues that will adversely impact performance of the system. The configuration of Flash memory system 10 imposes physical performance limitations. With the large number of parallel signals extending across the system, the signal integrity of the signals they carry will be degraded by crosstalk, signal skew, and simultaneous switching noise (SSN). Power consumption in such a configuration becomes an issue as each signal track between the flash controller and flash memory devices is frequently charged and discharged for signaling. With increasing system clock frequencies, the power consumption will increase.
There is also a practical limit to the number of memory devices which can be connected in parallel to the channel since the drive capability of a single memory device is small relative to the loading of the long signal tracks. Furthermore, as the number of memory devices increase, more chip enable signals (CE#) are required, and the clock signal CLK will need to be routed to the additional memory devices. Clock performance issues due to extensive clock distribution are well known in the art, which would need to be addressed. Therefore, in order to accommodate a memory system having a large number of memory devices, either a controller having more channels must be used, or and/or the system will need to be clocked at a lower frequency. A controller configured to have multiple channels and additional chip enable signals increases the cost of the memory system. Otherwise, the memory system is limited to a small number of memory devices.
It is, therefore, desirable to provide a memory system architecture capable of supporting any number of memory devices.